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Hardware Interface Description

Chip block diagram​

rk3566 block diagram

Radxa CM3 IO Board diagram​

cm3 io block diagram

Interface Preview​

cm3

Interface details​

The following outlines the comprehensive interface details for the Radxa CM3 IO Board:

BAT​

PinNamePinName
1BAT_3V7_PLUS2TS
3BAT_3V7_LOSE

DIP_2.54MM_3PIN_180​

  • U31

    PinNamePinName
    1WL_nDis2GND
    3BT_nDis

  • U32

    PinNamePinName
    1PWRON_KEY2GND
    3RUN_PG

EDP​

RK3566 integrates an eDP (Embedded DisplayPort) v1.3 controller, supporting data rates of 1.62Gbps/lane and 2.7Gbps/lane. It operates in 1-lane, 2-lane, and 4-lane modes, with a maximum output resolution of 2560x1600@60Hz. The eDP interface also includes an AUX channel with a maximum rate of 1Mbps.

For the coupled differential signals in the eDP interface, it is recommended to place a 100nF coupling capacitor near the transmitter. It is suggested to use capacitors with 0201 package size to reduce Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL).

  • eDP Interface Features:

    • Supports 1 eDP 1.3 interface
    • Supports up to 4 physical channels of 2.7Gbps
    • Supports Panel Self-Refresh (PSR)
    • Supports resolutions up to 2560x1600@60Hz
    • Supports up to 10-bit RGB format

  • Impedance and Description of eDP Interface Signals:

    SignalImpedanceDescription
    eDP_TX_DP/DN[3:0]100ohm±10%eDP TX data transmission, with 100nF capacitor
    eDP_TX_AUXP/N100ohm±10%eDP TX auxiliary channel, with 100nF capacitor
    eDP_HPDINN/ANo eDP TX insertion detection
    EDP

  • eDP Layout Requirements

    RangeRequirements
    Trace Impedance100Ω ±10% differential
    Max intra‑pair skew<12mil
    Max trace length on carrier board<6 inches
    Minimum pair to pair spacingRecommend ≥4 times the width of eDP trace
    AC coupling capacitors100nF ±20%, discrete 0201 package preferable
    Minimum spacing between eDP and other signals≥4 times the width of eDP trace
    Maximum allowed via Recommend≤ 4 vias

  • The trace length for the eDP (Embedded DisplayPort) signals on the compute module.

    SignalLength
    EDP_TX_AUXN1125.784mil
    EDP_TX_AUXP1145.200mil
    EDP_TX_D0N1,551.442mil
    EDP_TX_D0P1,605.627mil
    EDP_TX_D1N1,394.502mil
    EDP_TX_D1P1,387.683mil
    EDP_TX_D2N1,223.146mil
    EDP_TX_D2P1,278.783mil
    EDP_TX_D3N1,074.909mil
    EDP_TX_D3P1,092.072mil

    Note: On the connector end of the eDP display, it is recommended to reserve a 100k pull-down resistor for AUXP and a 100k pull-up resistor for AUXN.

Ethernet​

The Radxa CM3 board integrates the Gigabit PHY chip RTL8211F. The four sets of differential signals PHY1_MDI0, PHY1_MDI01, PHY1_MDI02, and PHY1_MDI03 are connected to a B2B connector. When operating at 1000BASE-T, all four sets of differential signals will be utilized. When operating at 100BASE-TX, only PHY1_MDI0 and PHY1_MDI01 will be used.

** Reference Schematic **

** Please refer to the schematic diagram for the specific signal definitions **

Ethernet Phy Design

The Radxa CM3 IO Board utilizes an integrated transformer and Ethernet port design. Please refer to the provided design reference as follows:

Ethernet Combo

The trace length for the MDI signals on the compute module.

SignalLength
PHY1_MDI0+319.903mil
PHY1_MDI0-326.000mil
PHY1_MDI1+249.671mil
PHY1_MDI1-277.370mil
PHY1_MDI2+394.321mil
PHY1_MDI2-400.440mil
PHY1_MDI3+335.779mil
PHY1_MDI3-347.346mil

For Gigabit Ethernet, the MDI (Medium Dependent Interface) differential signals are generally controlled to have a differential impedance around 100 ohms.

FAN​

PinNamePinName
1PMW0_M12+5V_INPUT
3GND4GND

HDMI​

HDMI (High-Definition Multimedia Interface) is a unified method of transmitting video and audio data to audio/video display devices through a TMDS (Transition Minimized Differential Signaling) compatible physical link. The HDMI interface is electrically compatible with the DVI (Digital Visual Interface) standard.

  • Features

    • HPD (Hot Plug Detect) input analog comparator
    • 13.5–600 MHz input reference clock range
    • Supports up to 10-bit deep color mode
    • Aggregate bandwidth up to 18Gbps
    • Supports video resolutions up to 1080p@120Hz and 4096x2304@60Hz
    • Compatibility with 3D video formats
    SignalImpedanceDescription
    HDMI_TX_DP/DN[2꞉0]100ohm±10%HDMI TX data transmission
    HDMI_TX_CLKP/CLKN100ohm±10%HDMI TX clock transmission
    HDMI_TX_HPDINNot specifiedHDMI TX hot‑plug detection
    HDMI_TX_REXTNot specifiedExternal resistor for HDMI reference connection(Default꞉ 1% precision 1.62k resistor)
    HDMITX_SCL/SDANot specifiedHDMI data communication channel
    HDMITX_CECNot specifiedHDMI Consumer Electronics Control pin

    On the Radxa CM3 compute module, the HDMITX_SCL/SDA and HDMITX_CEC signals have already gone through level translation processing. The HDMI_TX_HPDIN signal has a 100k ohm pull-down resistor and is connected in series with a 1k ohm resistor to the RK3566. When designing the baseboard, users don't need to worry about level translation issues. Please refer to the following design guide:

    HDMI Design

  • HDMI 2.0 Layout Requirements

    RangeRequirements
    Trace Impedance100Ω ±10% differential
    Max intra‑pair skew<12mil
    Max mismatch between clock and data pairs<480mil
    Max trace length on carrier board<6 inches
    Minimum pair to pair spacing≥5 times the width of HDMI trace (At least 4 times the width of HDMI trace)
    Minimum spacing between HDMI and other Signals≥5 times the width of HDMI trace (At least 4 times the width of HDMI trace)
    Maximum allowed viaRecommend ≤ 2 vias

  • The trace length for the HDMI signal on the compute module

    SignalLength
    HDMI_TX0N_PORT1310.556mil
    HDMI_TX0P_PORT1302.62mil
    HDMI_TX1N_PORT1218.286mil
    HDMI_TX1P_PORT1156.647mil
    HDMI_TX2N_PORT1122.794mil
    HDMI_TX2P_PORT1118.675mil
    HDMI_TXCLKN_PORT1437.63mil
    HDMI_TXCLKP_PORT1,398.265mil

MIPI CSI​

  • Camera_1

    PinNamePinName
    1VCC3V3_SYS2I2C0_SDA_PMIC
    3I2C0_SCL_PMIC4CAM_CLKOUT0
    5CAM_GPIO6GND
    7MIPI_CSI_RX_CLK0P8MIPI_CSI_RX_CLK0N
    9GND10MIPI_CSI_RX_D1P
    11MIPI_CSI_RX_D1N12GND
    13MIPI_CSI_RX_D0P14MIPI_CSI_RX_D0N
    15GND16GND
    17GND

  • Camera_2

    PinNamePinName
    1VCC3V3_SYS2I2C2_SDA_M1
    3I2C2_SCL_M14CAM_CLKOUT1
    5CAM_PWR_26GND
    7MIPI_CSI_RX_CLK1P8MIPI_CSI_RX_CLK1N
    9GND10MIPI_CSI_RX_D3P
    11MIPI_CSI_RX_D3N12GND
    13MIPI_CSI_RX_D2P14MIPI_CSI_RX_D2N
    15GND16GND
    17GND

MIPI DSI​

  • LCD_1

    PinNamePinName
    1VCC_LEDA12VCC_LEDA1
    3VCC_LEDA14GND
    5VCC_LEDK16VCC_LEDK1
    7VCC_LEDK18VCC_LEDK1
    9GND10GND
    11MIPI_DSI_TX0_D2P/LVDS_TX0_D2P12MIPI_DSI_TX0_D2N/LVDS_TX0_D2N
    13GND14MIPI_DSI_TX0_D1P/LVDS_TX0_D1P
    15MIPI_DSI_TX0_D1N/LVDS_TX0_D1N16GND
    17MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP18MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN
    19GND20MIPI_DSI_TX0_D0P/LVDS_TX0_D0P
    21MIPI_DSI_TX0_D0N/LVDS_TX0_D0N22GND
    23MIPI_DSI_TX0_D3P/LVDS_TX0_D3P24MIPI_DSI_TX0_D3N/LVDS_TX0_D3N
    25GND26Not Connected
    27MIPI_RESET_128GND
    29VCC_1V8_130VCC_LCD_MIPI
    31VCC_LCD_MIPI

  • LCD_2

    PinNamePinName
    1VCC_LCD_MIPI_22VCC_1V8_2
    3Not Connected4MIPI_RESET_2
    5Not Connected6GND
    7MIPI_DSI_TX1_D0N8MIPI_DSI_TX1_D0P
    9GND10MIPI_DSI_TX1_D1N
    11MIPI_DSI_TX1_D1P12GND
    13MIPI_DSI_TX1_CLKN14MIPI_DSI_TX1_CLKP
    15GND16MIPI_DSI_TX1_D2N
    17MIPI_DSI_TX1_D2P18GND
    19MIPI_DSI_TX1_D3N20MIPI_DSI_TX1_D3P
    21GND22GND
    23TP_RST_LCD24VCC_TP
    25TP_INT_LCD26I2C2_SDA_LCD
    27I2C2_SCL_LCD28GND
    29GND30VCC_LCD_MIPI_2
    31VCC_LCD_MIPI_232GND
    33GND34VCC_LEDK2
    35VCC_LEDK236Not Connected
    37Not Connected38VCC_LEDA2
    39VCC_LEDA240GND
    41VCC_LCD_MIPI_2

PCIe​

PinNamePinName
B1VCC12VA1Not Connected
B2VCC12VA2VCC12V
B3VCC12VA3VCC12V
B4GNDA4GND
B5Not ConnectedA5VCC3V3_PCIE
B6Not ConnectedA6VCC3V3_PCIE
B7GNDA7Not Connected
B8VCC3V3_PCIEA8VCC3V3_PCIE
B9VCC3V3_PCIEA9VCC3V3_PCIE
B10VCC3V3_PCIEA10VCC3V3_PCIE
B11PCIE20_WAKEnA11Pcie_nRST
B12PCIE20_CLKREQn_M2A12GND
B13GNDA13PCIE20_REFCLKP
B14PCIE20_TXP_1A14PCIE20_REFCLKN
B15PCIE20_TXN_1A15GND
B16GNDA16PCIE20_RXP_1
B17Not ConnectedA17PCIE20_RXP_1
B18GNDA18GND
C1Not ConnectedC2Not Connected

RTC​

rtc schematic

SATA​

SATA (Serial Advanced Technology Attachment) is a serial communication hard drive interface supported by RK3566. It supports the SATA 3 protocol and provides the following features:

  • Backward compatibility with SATA 1 and SATA 2.
  • Supports a maximum data channel signaling rate of 6GT/s.
  • Supports Out-of-Band (OOB) communication.
  • Supports SATA Power Management (PM) and external chip extension.
  • Supports spread spectrum function.

The table below provides the impedance and description of SATA interface signals:

SignalImpedanceDescription
SATAx_TXP/N90ohm±10%SATA data transmission, coupling capacitor 10nF placed near the motherboard connector
SATAx_RXP/N90ohm±10%SATA data reception, coupling capacitor 10nF placed near the motherboard connector

SATA 3.0: Consider the following layout requirements

ParameterRequirement
Line Impedance100Ω ±10% differential
Maximum intra-pair skew<1200 ps
Maximum trace length on the board<6 inches
AC coupling capacitor10nF ±20%, preferably using discrete 0201 package
Minimum spacing between pairs≥4 times the SATA trace width
Minimum spacing from SATA to other signals≥4 times the SATA trace width
Maximum allowed via countRecommended ≤ 2 vias

  • SATA3.0 Port2 J7

    PinNamePinName
    1GND2SATA1_TXP
    3SATA1_TXN4GND
    5SATA1_RXN6SATA1_RXP
    7GND8GND
    9SATA30_7P_V_DIP

  • SATA3.0 Port2 J20

    PinNamePinName
    1GND2SATA2_TXP
    3SATA2_TXN4GND
    5SATA2_RXN6SATA2_RXP
    7GND8GND
    9SATA30_7P_V_DIP

TP​

PinNamePinName
1TP_RST_L2VCC3V3_TP
3GND4TP_INT_L
5I2C3_SDA_TP6I2C3_SCL_TP
7GND8GND

USB​

  • USB2.0

    PinNamePinName
    1VCC5V0_USB12USB2_DM
    3USB2_DP4GND
    5VCC5V0_USB16USB1_DM
    7USB1_DP8GND
    9GND10GND
    11GND12GND

  • USB3.0

    PinNamePinName
    15V0_USB302USB3_HOST1_DM
    3USB3_HOST1_DP4GND
    5USB3_SSRXN6USB3_SSRXP
    7GND8USB3_SSTXN
    9USB3_SSTXP10GND
    11GND

40-PIN GPIO​

  • Voltage Range
TypeVoltageTolerance
GPIO3.3V3.63V
ADC1.8V1.98V
  • GPIO Interface

Radxa CM3 IO provides a 40 pin GPIO socket, which is compatible with most sensor applications on the market.

caution

Tips: The actual compatibility is subject to usage.

tip

Radxa CM3 IO Board and Raspberry Pi CM4 IO Baseboard's 40-pin expansion header are compatible. The following pinout applies to both products:

GPIO numberFunction4Function3Function2Function1Pin#Pin#Function1Function2Function3Function4GPIO number
+3.3V
1
2
+5.0V
14PWM2_M1SPI0_MOSI_M0I2C2_SDA_M0GPIO0_B6
3
4
+5.0V
13PWM1_M1SPI0_CLK_M0I2C2_SCL_M0GPIO0_B5
5
6
GND
125I2S1_SDI3_M1GPIO3_D5
7
8
GPIO0_D1
UART2_TX_M0
25
GND
9
10
GPIO0_D0
UART2_RX_M0
24
23UART0_CTSnPWM0_M1GPIO0_C7
11
12
GPIO3_C7I2S1_SCLK_TX_M1119
15PWM0_M0GPIO0_B7
13
14
GND
19PWM4GPIO0_C3
15
16
GPIO3_D4I2S1_SDI2_M1124
+3.3V
17
18
GPIO3_D3I2S1_SDI1_M1123
138I2C4_SDA_M0I2S2_SDI_M1SPI3_MOSI_M0GPIO4_B2
19
20
GND
136I2S1_SDO1_M1SPI3_MISO_M0GPIO4_B0
21
22
GPIO3_C6I2S1_MCLK_M1118
139I2C4_SCL_M0I2S2_SDO_M1SPI3_CLK_M0GPIO4_B3
23
24
GPIO4_A6SPI3_CS0_M0I2S1_SCLK_RX134
GND
25
26
GPIO4_C5UART9_TX_M1I2S3_SDO_M1SPI3_MISO_M1
140I2C2_SDA_M1GPIO4_B4
27
28
GPIO4_B5I2C2_SCL_M1I2S1_SDO3_M1141
137I2S1_SDO2_M1GPIO4_B1
29
30
GND
21PWM6SPI0_MISO_M0GPIO0_C5
31
32
GPIO4_C0PWM11_IR_M1144
22PWM7_IRSPI0_CS0_M0GPIO0_C6
33
34
GND
120I2S1_LRCK_TX_M1GPIO3_D0
35
36
GPIO4_A7I2S1_LRCK_RX_M1135
18PWM3_IRGPIO0_C2
37
38
GPIO3_D2I2S1_SDI0_M1122
GND
39
40
GPIO3_D1I2S1_SDO0_M1121

  • More details about 40-pin Header In V1.1

  • Pins marked with color orange are designed for debug console.

  • PWM: x8, PWM0 / PWM1 / PWM2 / PWM3 / PWM4 / PWM6 / PWM7 / PWM11

  • SPI: x2, SPI0 / SPI3

  • I2C: x2, I2C2 / I2C4

  • UART: x1, UART2